An active matrix-type display device selects two-dimensionally arranged pixel circuits in a unit of row, and writes voltages in accordance with display data into the selected pixel circuits, to display an image. For selecting the pixel circuits in a unit of row, there is used a shift register for sequentially shifting an output signal based on a clock signal, as a scanning line drive circuit. Further, in a display device for performing a dot sequential drive, a similar shift register is provided inside a data line drive circuit.
In a liquid crystal display device and the like, a drive circuit of pixel circuits may be integrally formed with the pixel circuits by using a manufacturing process for forming TFTs (Thin Film Transistors) in the pixel circuits. In this case, it is preferable to form a drive circuit including a shift register with transistors of the same conductive type as the TFTs.
As for the shift register, a variety of circuits have hitherto been proposed. FIG. 63 is a block diagram showing a configuration of a shift register described in Patent Document 1. The shift register shown in FIG. 63 is configured by connecting unit circuits 91 shown in FIG. 64 in multiple stages, and is operated in accordance with a timing chart shown in FIG. 65. In this shift register, a bootstrap method is adopted. Hereinafter, a threshold voltage of the transistor is referred to as Vth, and a high-level potential is referred to as VDD.
As an input signal IN, the unit circuit 91 is provided with an output signal OUT of the unit circuit 91 in the previous stage (or a start pulse ST). When the input signal IN shifts to a high level, a transistor Q2 is turned on, and a potential of a node N1 rises to (VDD−Vth). Next, when a clock signal CK changes from a low level to the high level, the potential of the node N1 rises to (VDD−Vth+α) by being pushed up by a capacitance between a gate and a channel of a transistor Q1 and a capacitor C1 (wherein α is substantially equal to the amplitude of the clock signal CK). Since “VDD−Vth+α>VDD+Vth” normally holds, when the clock signal CK passes through the transistor Q1, the high-level potential of the clock signal CK does not drop in an amount corresponding to a threshold voltage of the transistor Q1. Hence it is possible to output as the output signal OUT the high-level potential VDD without a threshold drop. Further, in the high-level period of the output signal OUT, a voltage between the gate and a source of the transistor Q1 becomes: (VDD−Vth+α)−VDD=α−Vth. By providing a potential sufficiently higher than the high-level potential of the clock signal CK to the gate terminal of the transistor Q1, it is possible to reduce rounding of the output signal OUT.